The present invention is in general related to switching devices. More particularly, embodiments of the present invention provide a method and a structure for a resistive switching device. The resistive switching device can be used in a non-volatile resistive switching memory device with random access and fast switching characteristics.
Semiconductor memory cells usually include a transistor device. Scaling of memory devices is therefore driven by reducing the size of the transistor. However, fundamental difficulties with scaling commonly used memory cells, such as those using floating gates, are driving the industry to examine a new memory cell structure that will allow scaling to ever smaller dimensions. New classes of memory devices being actively investigated include ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM). These devices usually attempt to use new materials and combine with silicon based devices to create a memory cell.
These new memory cells are often limited in certain desirable attributes. For example, shrinking the device size may not be not possible, or the device may lack high speed switching. For example, Fe-RAM and MRAM devices have fast switching characteristics but scaling them to small sizes is rather difficult. One of the factors that limits the ability to reduce MRAM size is the number of contacts, or terminals, needed to enable the device. A MRAM cell has at least three terminals. A MRAM cell containing at least one transistor coupled with a magnetic switch has a size of 16F2, or greater, where F is the printed feature size. For a PCRAM, in which switching occurs when a material is changed from a conductive polycrystalline phase to a less conductive amorphous phase, a relatively large amount of power is needed to switch the device, resulting in slow program/erase for large files. ORAM is usually incompatible with large volume silicon based fabrication. Key attributes of a memory cells should include: the ability to scale to a small size, fast switching speeds, low power consumption, low fabrication cost, long endurance (the ability to read, program, and erase the device multiple times without degradation), and compatibility with current large volume silicon fabrication processes, among others.
Because of these limitations, an improved semiconductor device structure for memory devices is therefore desirable.